RMS-to-DC converter with fault detection and recovery

ABSTRACT

A circuit that provides the root-mean-square (RMS) value of an input signal and that detects and independently recovers from an output fault condition is provided. The circuit includes reconfigurable circuitry that changes from normal operating mode to fault recovery mode when an output fault is detected. During fault recovery mode, the circuit provides a modified output signal that allows independent recovery from an output fault condition. Once recovery is complete, the circuit returns to normal operating mode and provides a DC output signal proportional to the RMS value of an AC input signal.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. patent application Ser.No. 09/736,068, filed Dec. 13, 2000, which is hereby incorporated byreference herein in its entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to apparatus and methods forproviding an output signal proportional to the root-mean-square (RMS)value of an input signal. More particularly, the present inventionrelates to apparatus and methods for detecting an output fault conditionand for recovering from such a condition so that an output signal isprovided. The output signal may be a direct current (DC) signalproportional to the RMS value of an input signal (commonly calledRMS-to-DC conversion).

[0003] The RMS value of a waveform is a measure of the heating potentialof that waveform. RMS measurements allow the magnitudes of all types ofvoltage (or current) waveforms to be compared to one another. Thus, forexample, applying an alternating current (AC) waveform having a value of1 volt RMS across a resistor produces the same amount of heat asapplying 1 volt DC voltage across the resistor.

[0004] Mathematically, the RMS value of a signal V is defined as:

V _(rms) ={square root}{square root over (V)} ²  (1)

[0005] which involves squaring the signal V, computing the average value(represented by the overbar in equation (1)), and then determining thesquare root of the result.

[0006] Various previously known conversion techniques have been used tomeasure RMS values. One previously known conversion system usesoversampling analog-to-digital converters to generate precise digitalrepresentations of an applied signal. The digital representations aredemodulated and filtered to produce a DC output signal that has the sameheat potential as the applied signal. This type of system is attractiveto circuit designers because it produces highly accurate results and canbe efficiently implemented on an integrated circuit.

[0007]FIG. 1 is a generalized schematic representation of a portion ofan RMS-to-DC converter circuit. As shown in FIG. 1, RMS-to-DC convertercircuit 30 includes pulse modulator 32, demodulator 34, gain stage 36,gain stage 38, and lowpass filter 54. Pulse modulator 32 has a firstinput coupled to VIN, a second input coupled to the output of gain stage38 and an output V₁. Demodulator 34 has an input coupled to V_(IN), acontrol input coupled to V₁, and an output V₂. Gain stage 38 has aninput coupled to V_(OUT), and provides a broadband gain B. Lowpassfilter 54 has an input coupled to V₂ and an output V₃ coupled to theinput of gain stage 36. Gain stage 36 has an output V_(OUT), andprovides a broadband gain A.

[0008] To simplify the description of pulse modulator 32 and demodulator34, the following discussion first assumes that A=B=1 (although inpractice it is common for A=B>1). As described below, this assumptiononly affects a scale factor in the resulting analysis. Pulse modulator32 may be any commonly known pulse modulator, such as a pulse codemodulator, pulse width modulator, or other similar modulator. As shownin FIG. 1, pulse modulator 32 is implemented as a single-bitoversampling ΔΣ pulse code modulator, and includes integrator 40,comparator 41, switch 42, non-inverting buffer 44, and inverting buffer46. As described in more detail below, switch 42 and buffers 44 and 46form a single-bit multiplying digital-to-analog converter (MDAC) 47.

[0009] Integrator 40 has a first input coupled to input V_(IN), a secondinput coupled to the pole of switch 42, and an output coupled to aninput of comparator 41. Comparator 41 has a clock input coupled to clocksignal CLK, and an output V₁ coupled to control terminals of switches 42and 52. Clock CLK is a fixed period clock that has a frequency that ismuch higher than the frequency of input V_(IN) (e.g., 100 timesgreater). Comparator 41 compares the signal at the output of integrator40 to a reference level (e.g., GROUND), and latches the comparisonresult as output signal V₁ on an edge of clock CLK.

[0010] Non-inverting buffer 44 provides unity gain (i.e., +1.0) and hasan input coupled to the output of gain stage 38, and an output coupledto the first terminal of switch 42. Inverting buffer 46 providesinverting gain (i.e., −1.0) and has an input coupled to the output ofgain stage 38, and an output coupled to the second terminal of switch42.

[0011] V₁ is a signal having a binary output level (e.g., −1 or +1). IfV₁=+1, the pole of switch 42 is coupled to the output of non-invertingbuffer 44. That is, (assuming gain B=1) +V_(OUT) is coupled to thesecond input of integrator 40. Alternatively, if V₁=−1, the pole ofswitch 42 is coupled to the output of inverting buffer 46. That is,(assuming gain B=1) −V_(OUT) is coupled to the second input ofintegrator 40. This switching configuration provides negative feedbackin pulse modulator 32.

[0012] The first and second inputs of integrator 40 therefore can havevalues equal to:

−V _(OUT) =V _(IN) =+V _(OUT)  (2)

[0013] and V_(IN) thus has a bipolar input signal range.

[0014] From equation (2), if V₁ has a duty ratio D between 0-100%, D canbe expressed as: $\begin{matrix}{{D = {\frac{1}{2} \times \left( {\frac{V_{IN}}{V_{OUT}} + 1} \right)}},{0 \leq D \leq 1}} & (3)\end{matrix}$

[0015] That is, if V_(IN)−V_(OUT), D=0, and if V_(IN)=+V_(OUT), D=1.

[0016] Demodulator 34 includes non-inverting buffer 48, inverting buffer50 and switch 52, which form a single-bit MDAC. Non-inverting buffer 48has an input coupled to V_(IN), and an output coupled to a firstterminal of switch 52. Inverting buffer 50 has an input coupled toV_(IN), and an output coupled to a second terminal of switch 52. Switch52 has a control terminal coupled to V₁ and a pole coupled to the inputof lowpass filter 54.

[0017] If V₁=+1, the pole of switch 52 is coupled to the output ofnon-inverting buffer 48. That is, +V_(IN) is coupled to the input oflowpass filter 54. Alternatively, if V₁=−1, the pole of switch 52 iscoupled to the output of inverting buffer 50. That is, −V_(IN) iscoupled to the input of lowpass filter 54.

[0018] Demodulator 34 provides an output signal V₂ at the pole of switch52 that may be expressed as: $\begin{matrix}{V_{2} = \quad {{{+ V_{IN}} \times D} - {\left( {- V_{IN}} \right) \times \left( {D - 1} \right)}}} & \text{(4a)} \\{\quad {= {V_{IN} \times \left( {{2 \times D} - 1} \right)}}} & \text{(4b)}\end{matrix}$

[0019] Substituting equation (3) into equation (4b), V₂ is given by:$\begin{matrix}{V_{2} = \frac{V_{IN}^{2}}{V_{OUT}}} & (5)\end{matrix}$

[0020] Lowpass filter 54 may be a continuous-time or a discrete-timefilter, and provides an output V₃ equal to the time average of input V₂.Accordingly, V₃ equals: $\begin{matrix}{V_{3} = \frac{\overset{\_}{V_{IN}^{2}}}{V_{OUT}}} & (6)\end{matrix}$

[0021] Gain stage 36 provides an output V_(OUT) equal to (assuming gainA=1) V₃: $\begin{matrix}{V_{OUT} = \frac{\overset{\_}{V_{IN}^{2}}}{V_{OUT}}} & \text{(7a)} \\{\quad {= {\sqrt{\overset{\_}{V_{IN}^{2}}} = V_{R\quad {MS}}}}} & \text{(7b)}\end{matrix}$

[0022] Thus, circuit 30 has a bipolar input range and provides an outputV_(OUT) equal to the RMS value of input V_(IN).

[0023] Demodulator 34 and stage 47 each are single-bit MDACs andcomparator 41 is a single-bit analog-to-digital converter (ADC) thatprovides a single-bit output V₁. The difference between the output ofintegrator 40 and MDAC 47 equals the quantization error e[i] of pulsemodulator 32.

[0024] Because the output of comparator 41 controls the polarity of thefeedback signal from V_(OUT) to the input integrator 40, converter 30will remain stable for only one polarity of V_(OUT). If V_(OUT) has apolarity opposite of that assumed for the connection of switch 42 (e.g.,during power up, a brown out, or a load fault), modulator 32 will becomeunstable, and the output of integrator 40 will quickly approach a railvoltage.

[0025] With a DC input, this may not be problematic, because the stateof V₁ might be such that V_(IN) propagates through MDAC 34 and resultsin the V₂ polarity desired for V_(OUT). In this case, once any externalinfluences on V_(OUT) are removed, V₂ (and therefore V_(OUT)), willreturn to the proper polarity once it propagates through low pass filter54. This sequence, however, has a probability of occurring only about50% of the time, meaning that converter 30 is unlikely to recover inalmost half of the possible DC operating cases. Moreover, RMS-to-DCconverters are most often used with AC signals, and in those instancesoutput recovery is even less likely to occur.

[0026] Thus, in view of the foregoing, it would be desirable to providemethods and apparatus for performing RMS-to-DC conversions that haveimproved recovery characteristics.

SUMMARY OF THE INVENTION

[0027] Accordingly, it is an object of this invention to provide methodsand apparatus for performing RMS-to-DC conversions that have faultdetection and recovery capabilities.

[0028] In accordance with this and other objects of the presentinvention, circuitry and methods that supply the root-mean-square (RMS)value of an input signal and that detect and independently recover fromoutput fault conditions are provided. The circuit of the presentinvention includes reconfigurable circuitry that changes from normaloperating mode to fault recovery mode when an output fault is detected.During fault recovery mode, the circuit of the present inventiongenerates a modified output signal that allows independent recovery froman output fault condition. Once recovery is complete, the circuitreturns to the RMS mode of operation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above-mentioned objects and features of the present inventioncan be more clearly understood from the following detailed descriptionconsidered in conjunction with the following drawings, in which the samereference numerals denote the same structural elements throughout, andin which:

[0030]FIG. 1 is a schematic diagram of a previously known RMS-to-DCconverter circuit;

[0031]FIG. 2A is a schematic diagram of an RMS-to-DC converter circuitof the present invention;

[0032]FIG. 2B is another schematic diagram of an RMS-to-DC convertercircuit of the present invention;

[0033]FIG. 3A is another schematic diagram of an RMS-to-DC convertercircuit of the present invention;

[0034]FIG. 3B is another schematic diagram of an RMS-to-DC convertercircuit of the present invention;

[0035]FIG. 4A is another schematic diagram of an RMS-to-DC convertercircuit of the present invention;

[0036]FIG. 4B is another schematic diagram of an RMS-to-DC convertercircuit of the present invention;

[0037]FIG. 5 is a schematic diagram of the reconfigurable AZ modulatorof FIGS. 2-4.

DETAILED DESCRIPTION OF THE INVENTION

[0038]FIG. 2A illustrates an embodiment of RMS-to-DC converterconstructed in accordance with the principles of the present invention.Circuit 130 includes pulse modulator 132, demodulator 134, gain stages36 and 38, lowpass filter 54, and optional delay-matching stage 82. Tosimplify the description of modulator 132 and demodulator 134, thefollowing discussion assumes that A=B=1 (although in practice it iscommon for A=B>1). This assumption only affects a scale factor in theresulting analysis.

[0039] Pulse modulator 132 includes cascaded AZ pulse code modulators.In particular, pulse modulator 132 includes reconfigurable ΔΣ stage 72,ΔΣ stage 76, monitor circuit 73, delay stage 78, and subtractor 80. Asdescribed in more detail below, ΔΣ stage 76, delay stage 78, andsubtractor 80 provide an estimate of the spectrally-shaped quantizationerror of reconfigurable ΔΣ stage 72.

[0040] Reconfigurable ΔΣ stage 72 has a first input coupled to V_(IN), asecond input coupled to the output of gain stage 38 (through switch 75),a first output coupled to the input of monitor circuit 73, and a secondoutput V₄ coupled to a first input of ΔΣ stage 76. ΔΣ stage 76 has asecond input coupled to the output of gain stage 38, and an output V₅coupled to a non-inverting input of subtractor 80 and to an input ofdelay stage 78. Subtractor 80 has an inverting input coupled to anoutput of delay stage 78, and an output V_(1b) coupled to a controlterminal of switch 96. Monitor circuit 73 may include a delay stage (notshown) to match the delay through ΔΣ stage 76, and has an output V_(1a)coupled to a control terminal of switch 88.

[0041] ΔΣ stages 72 and 76 may be, for example, single-bit modulatorsthat can be of any order. Preferably, reconfigurable ΔΣ stage 72 is afirst-order stage. Reconfigurable first-order ΔΣ stage 72 and monitorcircuit 73 provide output V_(1a) equal to (assuming gain B=1):$\begin{matrix}{{V_{1a}\left\lbrack {i + 1} \right\rbrack} = {\frac{\left( {V_{IN}\left\lbrack {i - 1} \right\rbrack} \right.}{V_{OUT}} + \frac{\left( {{e\lbrack i\rbrack} - {e\left\lbrack {i - 1} \right\rbrack}} \right)}{V_{OUT}}}} & (8)\end{matrix}$

[0042] where index i denotes the sample index and e[i] is thequantization error of reconfigurable ΔΣ stage 72. V_(1a) thus equals thedesired ratio of the input divided by V_(OUT), plus thespectrally-shaped quantization error of reconfigurable ΔΣ stage 72divided by V_(OUT).

[0043] ΔΣ stage 76, delay stage 78 and subtractor 80 provide an outputV_(1b) equal to an estimate of the spectrally-shaped quantization errorof reconfigurable ΔΣ stage 72 divided by V_(OUT). In particular, V4 isthe quantization error e[i] of reconfigurable ΔΣ stage 72, which is afunction of the input signal V_(IN), the state of the integrator, andthe local feedback within the MDAC of reconfigurable ΔΣ stage 72. ΔΣstage 76 provides an output V₅ equal to (assuming gain B=1):$\begin{matrix}{{V_{5}\left\lbrack {i + 1} \right\rbrack} = {\left( \frac{1}{V_{OUT}} \right) \times \left\lbrack {{e\lbrack i\rbrack} + \left( {{e^{\prime}\left\lbrack {i + 1} \right\rbrack} - {e^{\prime}\lbrack i\rbrack}} \right)} \right\rbrack}} & (9)\end{matrix}$

[0044] where e′[i] is the quantization error of ΔΣ stage 76. Delay stage78 and subtractor 80 form a digital differentiator that provide anoutput V_(1b) equal to (assuming gain B=1): $\begin{matrix}{{V_{1b}\left\lbrack {i + 1} \right\rbrack} = {\left( \frac{1}{V_{OUT}} \right) \times \left\lbrack {e_{1} + e_{2}} \right\rbrack}} & (10)\end{matrix}$

[0045] where

e ₁ =e[i]−e[i−1]  (11a)

e ₂ =e′[i+1]−2e′[i]+e′[i−1]  (11b)

[0046] Delay stage 82 matches the combined delay through pulse codemodulator 132. Demodulator 134 provides an output proportional to inputV_(IN) times the ratio of V_(IN) to V_(OUT). In particular, demodulator134 includes non-inverting buffer 84, inverting buffer 86, switch 88,subtractor 90, non-inverting buffer 92, inverting buffer 94,three-position switch 96 and multiply-by-two stage 97. Non-invertingbuffer 84 provides unity gain (i.e., +1.0) and has an input coupledthrough delay stage 82 to input V_(IN), and an output coupled to thefirst terminal of switch 88. Inverting buffer 86 provides inverting gain(i.e., −1.0) and has an input coupled through delay stage 82 to inputV_(IN), and an output coupled to the second terminal of switch 88.Non-inverting buffer 84, inverting buffer 86 and switch 88 form asingle-bit MDAC.

[0047] V_(1a) is a binary signal having a binary output level (e.g., −1or +1). If V_(1a)=+1, the pole of switch 88 is coupled to the output ofnon-inverting buffer 84. That is, +V_(IN) is coupled to first input V₆of subtractor 90. Alternatively, if V_(1a)=−1, the pole of switch 88 iscoupled to the output of inverting buffer 86. That is, −V_(IN) iscoupled to first input V₆ of subtractor 90. V₆ equals (assuming gainB=1) $\begin{matrix}{{V_{6}\left\lbrack {i + 1} \right\rbrack} = {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times {V_{1a}\left\lbrack {i + 1} \right\rbrack}}} & \left( {12a} \right) \\{\quad {= {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {{V_{IN}\left\lbrack {i - 1} \right\rbrack} + e_{1}} \right)}}} & \text{(12b)}\end{matrix}$

[0048] Non-inverting buffer 92 provides unity gain (i.e., +1.0) and hasan input coupled through delay stage 82 to input V_(IN), and an outputcoupled to the first terminal of three-position switch 96. Invertingbuffer 86 provides inverting gain (i.e., −1.0) and has an input coupledthrough delay stage 82 to input V_(IN), and an output coupled to thethird terminal of three-position switch 96. The second terminal ofthree-position switch 96 is coupled to GROUND. Non-inverting buffer 92,inverting buffer 94 and three-position switch 96 form a 1.5-bit MDAC.Multiply-by-two stage 97 provides a gain of +2.0.

[0049] V_(1b) is a tri-level signal having output values of −2, 0 or +2.If V_(1b)=+2, the pole of three-position switch 96 is coupled to theoutput of non-inverting buffer 92. That is, +2V_(IN) is coupled tosecond input V₇ of subtractor 90. If V_(1b)=0, the pole of switch 96 iscoupled to GROUND, and therefore 0 is coupled to second input V₇ ofsubtractor 90. If, however, V_(1b)=−2, the pole of switch 96 is coupledto the output of inverting buffer 94. That is, −2V_(IN) is coupled tosecond input V₇ of subtractor 90. V₇ equals (assuming gain B=1)$\begin{matrix}{{V_{7}\left\lbrack {i + 1} \right\rbrack} = {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {e_{1} + e_{2}} \right)}} & (13)\end{matrix}$

[0050] Subtractor 90 provides an output V₈ that equals the differencebetween V₆ and V₇: $\begin{matrix}{{V_{8}\left\lbrack {i + 1} \right\rbrack} = {{V_{6}\left\lbrack {i + 1} \right\rbrack} - {V_{7}\left\lbrack {i + 1} \right\rbrack}}} & \text{(14a)} \\{\quad {= {\frac{{V_{IN}\left\lbrack {i - 1} \right\rbrack}^{2}}{V_{OUT}} - {\frac{{V_{IN}\left\lbrack {i - 1} \right\rbrack}^{2}}{V_{OUT}} \times e_{2}}}}} & \text{(14b)}\end{matrix}$

[0051] Thus, V₈ is proportional to V_(IN) squared divided by V_(OUT),substantially without the quantization noise of reconfigurable ΔΣ stage72. The quantization noise e₂ of ΔΣ stage 76 remains, but the lowfrequency portion of that noise is further reduced by the spectralshaping provided by delay 78 and subtractor 80. Further, because e₂ isuncorrelated with V_(IN), the DC average of the product of e₂ and V_(IN)equals zero. As a result, output V₉ of lowpass filter 54 approximatelyequals:

V ₉ ≈{square root}{square root over (V_(IN) ²)}  (15)

[0052] Output V_(OUT) of gain stage 36 approximately equals (assuminggain A=1):

V _(OUT) ≈{square root}{square root over (V_(IN) ²)}  (16)

[0053] The circuit of FIG. 2A may be implemented using single-ended ordifferential circuitry.

[0054] During operation, output signals from reconfigurable ΔΣ stage 72may pass through monitor circuit 73 to the pole of switch 88. Asmentioned above, when V_(OUT) changes polarity, ΔΣ stages 72 and 76become unstable, producing a string of output bits with the same logiclevel. Monitor circuit 73, which may include counter circuits and/orlatch circuitry (not shown), detects this string and interprets it as a“fault condition.” In response to the detected fault condition, monitorcircuit 73 generates a control signal that causes circuit 130 to switchfrom RMS-to-DC conversion mode to fault recovery mode.

[0055] The number of consecutive same logic level bits that constitute afault condition may be varied if desired. For example, with certainmodulator topologies, the number of bits may be set to be relativelylong (e.g., about 50) to ensure circuit 130 does not enter recovery modeinadvertently. In other applications, however, the number of bits may besomewhat less (e.g., about 15) to reduce recovery time.

[0056] In fault recovery mode, switch 75 is opened, breaking thefeedback path from output V_(OUT) to ΔΣ stage 72. In addition, somecomponents within ΔΣ stage 72 are reconfigured so that ΔΣ stage 72functions as a comparator circuit rather than as a modulator circuit(shown as comparator circuit 77 in FIG. 2B).

[0057] With this arrangement, shown in FIG. 2B, circuit 130 operates asa mean-absolute-detect circuit instead of an RMS-to-DC converter.Circuit 130 thus determines the average of the absolute value of inputsignal V_(IN). Although this measurement is less meaningful than the RMSvalue of the input signal, it ensures circuit 130 will produce an outputsignal V_(OUT) that has the proper polarity. Once V_(OUT) returns to thecorrect polarity, the bit stream produced by ΔΣ stage 76 toggles,indicating that the fault condition has cleared. Monitor circuit 73detects this change of logic level and returns circuit 130 to RMS-to-DCconversion mode (i.e., closes switch 75 and reconfigures comparator 77to operate as ΔΣ stage 72). In this way, circuit 130 may detect andrecover from fault conditions irrespective of the type and amplitude ofinput signal V_(IN).

[0058] As shown in FIG. 2B, to operate as a mean-absolute-detectcircuit, the feedback from V_(OUT) to comparator 77 is disconnected. Theoutput signal produced by comparator 77 is a bit stream that representsthe polarity of input signal V_(IN). Comparator 77 may be configured asa polarity detector using any suitable arrangement known in the art(e.g., by connecting a threshold terminal to ground and a sensingterminal (both not shown) to input signal V_(IN))

[0059] When the output of comparator 77 is provided to demodulator 134(i.e., the pole of switch 88), the input signal V_(IN) is multiplied byits own polarity, thus performing an absolute value operation. Theresulting signal is then fed through lowpass filter 54 which provides anoutput signal V_(OUT) of the desired polarity (assuming any externalstimuli has been removed from the output node).

[0060] As long as output signal V_(OUT) is the incorrect polarity, ΔΣstage 76 will be unstable, and its output will remain at either a logiclow or a logic high (depending on its state when the output faultoccurred). When this occurs, subtractor 80 has a substantially zerooutput and will not affect the value of V_(OUT).

[0061] When circuit 130 is operating in mean-absolute-detect mode, errorsignal V₄ produced by comparator 77 is the input signal V_(IN) (or ascaled version thereof). Thus, the output of ΔΣ stage 76 can bemonitored (by monitor circuit 73) to determine when recovery from anoutput fault has occurred. For example, when the bit stream produced byΔΣ stage 76 toggles from one logic state to another, circuit 130 hasrecovered from the fault condition and may be reconfigured back to theRMS-to-DC converter shown in FIG. 2A.

[0062] The overall gain of circuit 130 during fault recovery (i.e.,mean-absolute-detect mode) does not need to be similar to that of theRMS-to-DC mode (i.e., normal operation). However, increased gain duringfault recovery does tend to reduce recovery time. Moreover, it will beunderstood that with certain input waveforms and filter time constants,circuit 130 may go into fault recovery, back to normal operation, andreturn to fault recovery several times in succession. As long as theoutput is free of external influences however, circuit 130 will recover.The successive fault mode periods will become shorter in duration untilcircuit 130 has fully recovered.

[0063]FIG. 3A shows another illustrative embodiment of RMS-to-DCconverter constructed in accordance with the present invention.Converter 230 includes single-sample delay stages 82 and 104, modulator232 and demodulator 234. Modulator 232 includes single-bitreconfigurable ΔΣ stage 72, ΔΣ stage 76, and monitor circuit 73, anddemodulator 234 includes single-bit MDAC stages 98, 100 and 102, andadder/subtractor 106. MDACS 98, 100, and 102 may be implemented as indemodulator 34 of FIG. 1. Alternatively, some of MDACS 98, 100 and 102may be implemented as a single time-multiplexed MDAC.

[0064] Reconfigurable ΔΣ stage 72 provides a quantized output V_(1c)equal to (assuming gain B=1): $\begin{matrix}{{V_{1c}\lbrack i\rbrack} = \frac{{V_{IN}\left\lbrack {i - 1} \right\rbrack} + {e\lbrack i\rbrack} - {e\left\lbrack {i - 1} \right\rbrack}}{V_{OUT}}} & (17)\end{matrix}$

[0065] In addition, V₄ equals the quantization error e[i] ofreconfigurable ΔΣ stage 72.

[0066] ΔΣ stage 76 provides a quantized output V_(1d) equal to (assuminggain B=1): $\begin{matrix}{{V_{1d}\lbrack i\rbrack} = \frac{{e\left\lbrack {i - 1} \right\rbrack} + {e^{\prime}\lbrack i\rbrack} - {e^{\prime}\left\lbrack {i - 1} \right\rbrack}}{V_{OUT}}} & (18)\end{matrix}$

[0067] Single-bit DACs 98, 100 and 102 provide outputs V₁₀, V₁₁ and V₁₂,respectively, equal to (assuming gain B=1):

V ₁₀ [i]=V _(IN) [i−1]×V _(1c) [i]  (19)

V ₁₁ [i]=V _(IN) [i−1]×V _(1d) [i]  (20)

V ₁₂ [i]=V _(IN) [i−2]×V _(1d) [i]  (21)

[0068] Adder/subtractor 106 provides an output V₁₃ equal to:

V ₁₃ [i]=V ₁₀ [i]+V ₁₁ [i]−V ₁₂ [i]  (22)

[0069] which equals (assuming gain B=1): $\begin{matrix}{{V_{13}\lbrack i\rbrack} = {{\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {{V_{IN}\left\lbrack {i - 1} \right\rbrack} + {e\lbrack i\rbrack} + {e^{\prime}\lbrack i\rbrack} - {e^{\prime}\left\lbrack {i - 1} \right\rbrack}} \right)} - {\frac{V_{IN}\left\lbrack {i - 2} \right\rbrack}{V_{OUT}} \times \left( {{e\left\lbrack {i - 1} \right\rbrack} + {e^{\prime}\lbrack i\rbrack} - {e^{\prime}\left\lbrack {i - 1} \right\rbrack}} \right)}}} & (23)\end{matrix}$

[0070] Note that: $\begin{matrix}{{V_{13}\left\lbrack {i + 1} \right\rbrack} = {{\frac{V_{IN}\lbrack i\rbrack}{V_{OUT}} \times \left( {{V_{IN}\lbrack i\rbrack} + {e\left\lbrack {i + 1} \right\rbrack} + {e^{\prime}\left\lbrack {i + 1} \right\rbrack} - {e^{\prime}\lbrack i\rbrack}} \right)} - {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {{e\lbrack i\rbrack} + {e^{\prime}\left\lbrack {i + 1} \right\rbrack} - {e^{\prime}\lbrack i\rbrack}} \right)}}} & (24)\end{matrix}$

[0071] If the time constant of lowpass filter 54 is much greater thanthe sample period of V₁₃[i] (e.g., 10,000 times), lowpass filter 54provides output V₁₄ that is the average of sequence V₁₃. V₁₃ as afunction of V_(IN)[i−1] approximately equals: $\begin{matrix}{V_{13}{{{V_{IN}\left\lbrack {i - 1} \right\rbrack} \approx {{\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {{V_{IN}\left\lbrack {i - 1} \right\rbrack} + {e\lbrack i\rbrack} + {e^{\prime}\lbrack i\rbrack} - {e^{\prime}\left\lbrack {i - 1} \right\rbrack}} \right)} - {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {{e\lbrack i\rbrack} + {e^{\prime}\left\lbrack {i + 1} \right\rbrack} - {e^{\prime}\lbrack i\rbrack}} \right)}}}}} & (25)\end{matrix}$

[0072] which may be written as: $\begin{matrix}{V_{13}{{{V_{IN}\left\lbrack {i - 1} \right\rbrack} = {\left( \frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \right)^{2} - \frac{{V_{IN}\left\lbrack {i - 1} \right\rbrack} \times \left( {{e^{\prime}\left\lbrack {i + 1} \right\rbrack} - {2{e^{\prime}\lbrack i\rbrack}} + {e^{\prime}\left\lbrack {i - 1} \right\rbrack}} \right)}{V_{OUT}}}}}} & (26)\end{matrix}$

[0073] The first term on the right side of equation (26) is the desiredoutput, and the second term equals the second-order spectrally-shapedquantization noise of ΔΣ stage 76, which is substantially reduced bylowpass filter 54. Further, because e′ is uncorrelated with V_(IN), theDC average of the product of e′ and V_(IN) equals zero. As a result, V₁₄approximately equals: $\begin{matrix}{V_{14} = {\overset{\_}{V_{13}} \approx \frac{\overset{\_}{V_{IN}^{2}}}{V_{OUT}}}} & (27)\end{matrix}$

[0074] Output V_(OUT) of gain stage 36 approximately equals (assuminggain A=1):

V _(OUT) ≈{square root}{square root over (V_(IN) ²)}  (28)

[0075] The circuit of FIG. 3A may be implemented using single-ended ordifferential circuitry.

[0076] During operation, output signals from reconfigurable ΔΣ stage 72may pass through monitor circuit 73 to MDAC 98. As mentioned above, whenV_(OUT) changes polarity, ΔΣ stages 72 and 76 become unstable, producinga string of output signals with a constant logic level. Monitor circuit73 detects this output string, which it interprets as a “faultcondition” and generates a control signal that causes circuit 230 toswitch from RMS-to-DC conversion mode to fault recovery mode.

[0077] In fault recovery mode, switch 75 is opened, breaking thefeedback path from output V_(OUT) to ΔΣ stage 72. Additionally, somecomponents within ΔΣ stage 72 are reconfigured so that ΔΣ stage 72functions as a comparator circuit rather than as a modulator circuit(shown as comparator circuit 77 in FIG. 3B).

[0078] In this arrangement, shown in FIG. 3B, circuit 230 operates as amean-absolute-detect circuit instead of an RMS-to-DC converter. Circuit230 thus determines the average of the absolute value of the inputsignal. Although this measurement is less meaningful than the RMS valueof the input signal, it ensures circuit 230 will produce an outputsignal V_(OUT) that has the proper polarity. Once V_(OUT) returns to theproper polarity, the bit stream produced by comparator 77 toggles,indicating that the fault condition has cleared. Monitor circuit 73detects this change of logic level and returns circuit 230 back toRMS-to-DC conversion mode (i.e., closes switch 75 and reconfigurescomparator 77 to operate as ΔΣ stage 72). In this way, circuit 230 maydetect and recover from fault conditions irrespective of the type andamplitude of input signal V_(IN).

[0079] As shown in FIG. 3B, to operate as a mean-absolute-detectcircuit, the feedback from V_(OUT) to comparator 77 is disconnected. Theoutput signal produced by comparator 77 is a bit stream that representsthe polarity of input signal V_(IN). Comparator 77 may be configured asa polarity detector using any suitable method known in the art (e.g., byconnecting a threshold terminal to ground and a sensing terminal (bothnot shown) to input signal V_(IN)).

[0080] When the output of comparator 77 is provided to demodulator 234(i.e., MDAC 98), input signal V_(IN) is multiplied by its own polarity,thus performing an absolute value operation. The resulting signal is fedthrough lowpass filter 54 which generates an output signal (V_(OUT)) ofthe desired polarity (assuming any external stimuli has been removedfrom the output node).

[0081] As long as output signal V_(OUT) is the incorrect polarity, ΔΣstage 76 will remain unstable. Its output will therefore remain ateither a logic low or a logic high (depending on its state when theoutput fault occurred). When this occurs, V₁₁ and V₁₂ substantiallycancel each other out (at summing node 106), and thus output V₁₃ issubstantially equal to the value of V₁₀. Alternatively, V₁₁ and V₁₂ maybe disconnected from summer 106 during fault recovery.

[0082] When circuit 230 is operating as a mean-absolute-detector, errorsignal V₄ produced by comparator 77 is the input signal V_(IN) (or ascaled version thereof). Thus, the output of ΔΣ stage 76 can bemonitored (by monitor circuit 73) to determine when recovery from anoutput fault has occurred. For example, when the bit stream produced byΔΣ stage 76 toggles from one logic state to another, indicating a changein output polarity, circuit 230 has recovered from the fault conditionand may be reconfigured back to the RMS-to-DC converter shown in FIG.3A.

[0083] The overall gain of circuit 230 during fault recovery (i.e.,mean-absolute-detect mode) does not need to be similar to that of theRMS-to-DC mode (normal operation). However, increased gain during faultrecovery does tend to reduce recovery time. Moreover, it will beunderstood that with certain input waveforms and filter time constants,circuit 230 may go into fault recovery, back to normal operation, andback to fault recovery several times in succession. As long as theoutput is free of external influences however, circuit 230 will recover.The successive fault mode periods will become shorter in duration untilcircuit 230 has fully recovered.

[0084]FIG. 4A illustrates another embodiment of RMS-to-DC convertersconstructed in accordance with the principles of the present invention.Circuit 330 includes delay stages 82 and 104 and pulse modulator 332 anddemodulator 334. Circuit 330 includes features of circuits 130 and 230,but substantially eliminates the effect of any DC offset that may occurin ΔΣ stage 76 and delay stage 104.

[0085] Modulator 332 includes single-bit reconfigurable ΔΣ stage 72 andΔΣ stage 76, delay stage 78, and subtractor 80. Demodulator 334 includes1-bit DAC 87, 1.5-bit DAC 89 (which may be constructed similar to theDAC formed by buffers 92 and 94 and switch 96), subtractor 90, andmultiply-by-two stage 97. Delay stage 82 matches the delay throughreconfigurable AZ modulator 72 and delay stage 104 matches the delaythrough ΔΣ modulator 76.

[0086] Reconfigurable ΔΣ stage 72 provides a quantized output V_(1e)equal to (assuming gain B=1) $\begin{matrix}{{V_{1e}\lbrack i\rbrack} = \frac{{V_{IN}\left\lbrack {i - 1} \right\rbrack} + {e\lbrack i\rbrack} - {e\left\lbrack {i - 1} \right\rbrack}}{V_{OUT}}} & (29)\end{matrix}$

[0087] ΔΣ stage 76, delay stage 78 and subtractor 80 provide an outputV_(1f) equal to an estimate of the spectrally-shaped quantization errorV₄ of reconfigurable ΔΣ stage 72 divided by V_(OUT). ΔΣ stage 76provides an output V₁₅ equal to (assuming gain B=1): $\begin{matrix}{{V_{15}\left\lbrack {i + 1} \right\rbrack} = {\left( \frac{1}{V_{OUT}} \right) \times \left\lbrack {{e\lbrack i\rbrack} + \left( {{e^{\prime}\left\lbrack {i + 1} \right\rbrack} - {e^{\prime}\lbrack i\rbrack}} \right)} \right\rbrack}} & (30)\end{matrix}$

[0088] where e′[i] is the quantization error of ΔΣ stage 76. Delay stage78 and subtractor 80 form a digital differentiator that provide anoutput V_(1f) equal to (assuming gain B=1): $\begin{matrix}{{V_{1f}\quad\left\lbrack {i + 1} \right\rbrack} = \left. {\left( \frac{1}{V_{OUT}} \right) \times} \middle| {e_{1} + e_{2}} \right|} & (31)\end{matrix}$

[0089] where

e ₁ =e[i]−e[i−1]  (32a)

e ₂ =e′[i+1]−2e′[i]+e′[i−1]  (32b)

[0090] V₁₆ equals (assuming gain B=1) $\begin{matrix}{{V_{16}\lbrack i\rbrack} = {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times {V_{1e}\lbrack i\rbrack}}} & \left( {33a} \right) \\{\quad {= {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {{V_{IN}\left\lbrack {i - 1} \right\rbrack} + e_{1}} \right)}}} & \left( {33b} \right)\end{matrix}$

[0091] V₁₇ equals (assuming gain B=1) $\begin{matrix}{{V_{17}\left\lbrack {i + 1} \right\rbrack} = {\frac{V_{IN}\left\lbrack {i - 1} \right\rbrack}{V_{OUT}} \times \left( {e_{1} + e_{2}} \right)}} & (34)\end{matrix}$

[0092] The digital differentiator formed by delay stage 78 andsubtractor 80 has a zero at DC, and therefore sequence V_(1f)substantially has no DC component. As a result, sequence V₁₇ issubstantially free of any DC offset introduced by delay stages 82 and104, and ΔΣ stage 76.

[0093] Subtractor 90 provides an output V₁₈ that equals the differencebetween V₁₆ and V₁₇: $\begin{matrix}{{V_{18}\left\lbrack {i + 1} \right\rbrack} = {{V_{16}\lbrack i\rbrack} - {V_{17}\left\lbrack {i + 1} \right\rbrack}}} & \left( {35a} \right) \\{\quad {= {\frac{{V_{IN}\left\lbrack {i - 1} \right\rbrack}^{2}}{V_{OUT}} - {\frac{V_{IN}}{V_{OUT}} \times e_{2}}}}} & \left( {35\quad b} \right)\end{matrix}$

[0094] Thus, V₁₈ is proportional to V_(IN) squared divided by V_(OUT),substantially without the quantization noise of Δ−Σ stage 72. Output V₁₉of lowpass filter 54 approximately equals:

V ₁₉ ≈{square root}{square root over (V_(IN) ²)}  (36)

[0095] and output V_(OUT) of gain stage 36 approximately equals(assuming gain A=1):

V _(OUT) ≈{square root}{square root over (V_(IN) ²)}  (37)

[0096] The circuit of FIG. 4A may be implemented using single-ended ordifferential circuitry.

[0097] During operation, output signals from reconfigurable ΔΣ stage 72may pass through monitor circuit 73 to MDAC 87. As mentioned above, whenV_(OUT) changes polarity, ΔΣ stages 72 and 76 become unstable, producinga string of output signals with a constant logic level. Monitor circuit73 detects this output string, which it interprets as a “faultcondition” and generates a control signal that causes circuit 330 toswitch from RMS-to-DC conversion mode to fault recovery mode.

[0098] In fault recovery mode, switch 75 is opened, breaking thefeedback path from output V_(OUT) to ΔΣ stage 72. Additionally, somecomponents within ΔΣ stage 72 are reconfigured so that ΔΣ stage 72functions as a comparator circuit rather than as a modulator circuit(shown as comparator circuit 77 in FIG. 4B).

[0099] In this arrangement, shown in FIG. 4B, circuit 330 operates as amean-absolute-detect circuit instead of an RMS-to-DC converter. Circuit330 thus determines the average of the absolute value of the inputsignal. Although this measurement is less meaningful than the RMS valueof the input signal, it ensures circuit 330 will produce an outputsignal V_(OUT) that has the proper polarity. Once V_(OUT) returns to theproper polarity, the bit stream produced by comparator 77 toggles,indicating that the fault condition has cleared. Monitor circuit 73detects this change of logic level and returns circuit 330 back toRMS-to-DC conversion mode (i.e., closes switch 75 and reconfigurescomparator 77 to operate as ΔΣ stage 72). In this way, circuit 330 maydetect and recover from fault conditions irrespective of the type andamplitude of input signal V_(IN).

[0100] As shown in FIG. 4B, to operate as a mean-absolute-detectcircuit, the feedback from V_(OUT) to comparator 77 is disconnected. Theoutput signal produced by comparator 77 is a bit stream that representsthe polarity of input signal V_(IN). Comparator 77 may be configured asa polarity detector using any suitable method known in the art (e.g., byconnecting a threshold terminal to ground and a sensing terminal (bothnot shown) to input signal V_(IN)).

[0101] When the output of comparator 77 is provided to demodulator 334(i.e., MDAC 87), input signal V_(IN) is multiplied by its own polarity,thus performing an absolute value operation. The resulting signal is fedthrough lowpass filter 54 which generates an output signal (V_(OUT)) ofthe desired polarity (assuming any external stimuli has been removedfrom the output node).

[0102] As long as output signal V_(OUT) is the incorrect polarity, ΔΣstage 76 will remain unstable. Its output will therefore remain ateither a logic low or a logic high (depending on its state when theoutput fault occurred). In this case, subtractor 80 will have asubstantially zero output and will not affect the value of V_(OUT).

[0103] When circuit 330 is operating as a mean-absolute-detect circuit,error signal V₄ produced by comparator 77 is the input signal V_(IN) (ora scaled version thereof). Thus, the output of ΔΣ stage 76 can bemonitored (by monitor circuit 73) to determine when recovery from anoutput fault has occurred. For example, when the bit stream produced byΔΣ stage 76 toggles from one logic state to another, indicating theoutput has changed polarity, circuit 330 has recovered from the faultcondition and may be reconfigured back to the RMS-to-DC converter shownin FIG. 4A.

[0104] The overall gain of circuit 330 during fault recovery (i.e.,mean-absolute-detect mode) does not need to be similar to that of theRMS-to-DC mode (normal operation). However, increased gain during faultrecovery does tend to reduce recovery time. Moreover, it will beunderstood that with certain input waveforms and filter time constants,circuit 330 may go into fault recovery, back to normal operation, andback to fault recovery several times in succession. As long as theoutput is free of external influences however, circuit 330 will recover.The successive fault mode periods will become shorter in duration untilcircuit 330 has fully recovered.

[0105] As mentioned above, monitoring circuit 73 may detect an outputfault by detecting a string of same logic level output bits fromreconfigurable ΔΣ stage 72. This will occur anytime reconfigurable ΔΣstage 72 is overloaded, either because it is unstable or because theinput signal V_(IN) is excessively large. Thus, under certaincircumstances a fault condition may be detected even when the outputsignal V_(OUT) is the “correct” polarity.

[0106] One such case is when the amplitude of the input signal (V_(IN))increases suddenly. For example, a step change of about a factor of tenmay cause reconfigurable ΔΣ stage 72 to overload and produce an outputduty cycle of either 0% or 100% at the peaks of the input waveform. Thisresult is acceptable and even desirable because it tends to decrease theoutput response time.

[0107] Another case during which a fault condition may be detected iswhen input signal V_(IN) has a large peak value with respect to the DClevel of the output signal V_(OUT) (e.g., this may occur with inputsignals V_(IN) having a high crest factor). Such an input signal may,during its peak, cause reconfigurable ΔΣ stage 72 to produce an outputhaving a duty cycle of either 0% or 100%. Depending on the duration ofthe peak and the length of the output string detected by monitor circuit73, this may initiate entry into the fault recovery mode of operation.This will increase the magnitude of the output signal V_(OUT) during atime when it otherwise would be underestimated.

[0108]FIG. 5 is a schematic diagram of one possible embodiment ofreconfigurable ΔΣ stage 72. In FIG. 5, reconfigurable ΔΣ stage 72, shownas system 500, includes switches 501-508, capacitors 510-517, amplifier518, and comparator 519. As mentioned above, system 500 may beconfigured to operate as either AZ modulator 72 or as comparator 77,depending on the state (i.e., open or closed) of switches 501-508.

[0109] When configured as ΔΣ stage 72, system 500 progresses throughessentially two phases of operation, an auto-zero phase and integrationphase. In auto-zero phase, switches 501, 506, and 508 are closed. Inaddition, either switches 503 or 504 are closed depending on the outputof comparator 519. For example, if the output of comparator 519 is alogic high, switches 504 may be closed and switches 503 may be open.Alternatively, if the output of comparator 519 is a logic low, switches504 may be open and switches 503 may be closed.

[0110] Input voltage V_(IN) is applied to node 520 and node 522 isconnected to ground (if desired, node 522 may be used as a differentialinput). In the arrangement shown, capacitor 510 is charged to the valueof input voltage V_(IN), and capacitor 511 is set to ground. Assumingfor the sake of illustration, that switches 503 are closed and switches504 are open, capacitor 512 is charged to the value of V_(OUT) andcapacitor 513 is set to ground.

[0111] Closing switches 506 provides a feedback path from outputs 532and 536 of amplifier 518 to inputs 530 and 534, respectively. This setsthe gain of amplifier 518, which is preferably a differentialtransconductance amplifier, to unity. At this point, system 500 hasacquired the values of both the input and output voltages and is readyto proceed to the integration phase of operation.

[0112] In the integration phase, switches 501 and 506 are opened andswitches 502 and 505 are closed, configuring amplifier 518 as anintegrator. Furthermore, the state of switches 503 or 504 areinterchanged. That is, if switches 503 were closed and switches 504 wereopen during auto-zero, switches 503 open and switches 504 close duringintegration (and vice versa). This transfers the charge from capacitors510-513 to capacitors 515 and 516, respectively. Thus, the resultingcharge on capacitors 515 and 516 is now equal to the transferred chargeplus any charge from the previous integration phase. Amplifier 518generates a differential output at terminals 532 and 536 which is afunction of the result of the previous integration phase, the value ofV_(IN) and V_(OUT), and the output state of comparator 519. Comparator519, which is preferably a latching comparator, compares these valuesand generates an output signal based on the comparison.

[0113] When configured as comparator stage 77, system 500 also operatesin essentially two phases of operation, an auto-zero phase and a sampleand hold phase. In auto-zero phase, switches 501, 506, and 508 areclosed. In addition, either switches 503 or 504 are closed.

[0114] Input voltage V_(IN) is applied to node 520 and node 522 isconnected to ground. In this arrangement, capacitor 510 is charged tothe value of input voltage V_(IN), and capacitor 511 is set to ground.Closing switches 506 provides a feedback path from outputs 532 and 536of amplifier 518 to inputs 530 and 534, respectively. This sets the gainof amplifier 518 to unity. At this point, system 500 has acquired thevalues of both the input and output voltages and is ready to proceed tothe sample and hold phase of operation.

[0115] In the sample and hold phase, switches 501 and 506 are opened andswitches 502 and 507 are closed, configuring amplifier 518 as a buffer.In this mode the state of switches 503 or 504 are preferably notinterchanged. The charge from capacitors 510 and 511 (but not 512 and513) is transferred to capacitors 514 and 517, respectively. Thus, theresulting charge on capacitors 514 and 517 is now substantially equal tothe input voltage V_(IN). Amplifier 518 generates a differential outputat terminals 532 and 536 based on VIN, which is provided to inputterminals 540 and 542 of comparator 519. Comparator 519 compares thesevalues and generates an output signal based on the comparison.

[0116] Persons skilled in the art will recognize that the apparatus ofthe present invention may be implemented using circuit configurationsother than those shown and discussed above. All such modifications arewithin the scope of the present invention, which is limited only by theclaims that follow.

What is claimed is:
 1. A circuit for providing an output signalproportional to a root-mean-square (RMS) value of an input signal thatis capable of detecting and independently recovering from an outputfault condition, the circuit comprising: a pulse code modulator circuitincluding a reconfigurable circuit coupled to an input node and anoutput node that may be reconfigured as a first delta-sigma modulatorcircuit and a comparator circuit; and a demodulator circuit including afirst multiplying digital to analog converter (MDAC) circuit.
 2. Thecircuit of claim 1 wherein said pulse code modulator circuit furthercomprises a second delta-sigma modulator circuit coupled to a firstoutput of the first delta-sigma modulator circuit and to the outputnode.
 3. The circuit of claim 2 wherein said pulse code modulatorcircuit further comprises a digital differentiator circuit coupled to afirst output of the second delta-sigma modulator circuit.
 4. The circuitof claim 3 further comprising a first delay circuit coupled to the inputnode and the first MDAC circuit.
 5. The circuit of claim 4 wherein saiddemodulator circuit further comprises a second MDAC circuit coupled tothe first delay circuit and to an output of the digital differentiatorcircuit, and a subtractor circuit coupled to an output of the first MDACcircuit, an output of the second MDAC circuit, and the output node. 6.The circuit of claim 1 further comprising a monitor circuit coupled toan output of said first delta-sigma modulator circuit that monitors theoutput of said first delta-sigma modulator circuit to determine when thefault condition occurs.
 7. The circuit of claim 2 further comprising amonitor circuit coupled to an output of said second delta-sigmamodulator circuit that monitors the output of said second delta-sigmamodulator circuit to determine when the circuit recovers from the faultcondition.
 8. The circuit of claim 5 further comprising a monitorcircuit coupled to the first MDAC circuit and a second output of saidfirst delta-sigma modulator circuit that monitors the output of saidfirst delta-sigma modulator circuit to determine when the faultcondition occurs.
 9. The circuit of claim 5 further comprising a monitorcircuit coupled to the first MDAC circuit and a second output of saidsecond delta-sigma modulator circuit that monitors the second output ofsaid second delta-sigma modulator circuit to determine when the circuitrecovers from the fault condition.
 10. The circuit of claim 8 whereinthe monitor circuit is further coupled to a second output of the seconddelta-sigma modulator circuit.
 11. The circuit of claim 9 wherein themonitor circuit is further coupled to a second output of the firstdelta-sigma modulator circuit.
 12. The circuit of claim 10 wherein saiddemodulator circuit further comprises a multiplier coupled between theoutput of the second MDAC circuit and the subtractor circuit.
 13. Thecircuit of claim 12 further comprising a second delay circuit coupled tothe first delay circuit and the second MDAC circuit.
 14. The circuit ofclaim 2 further comprising a monitor circuit coupled to a second outputof said first delta-sigma modulator circuit and to an output of saidsecond delta-sigma modulator circuit, wherein at least one of theconditions from the group consisting of the following is true: 1) themonitor circuit monitors the second output of said first delta-sigmamodulator circuit to determine when the fault condition occurs and 2)the monitor circuit monitors the output of said second delta-sigmamodulator circuit to determine when the circuit recovers from the faultcondition.
 15. The circuit of claim 2 further comprising a first delaycircuit coupled to the input node and the first MDAC circuit.
 16. Thecircuit of claim 15 wherein said demodulator circuit further comprises asecond MDAC circuit coupled to the first delay circuit and to a firstoutput of the second delta-sigma modulator circuit, a third MDAC circuitcoupled to the first delay circuit and to the first output of the seconddelta-sigma modulator circuit, and a subtractor circuit coupled to anoutput of the first MDAC circuit, an output of the second MDAC circuit,an output of the third MDAC circuit, and the output node.
 17. Thecircuit of claim 16 further comprising a second delay circuit coupled tothe first delay circuit and the third MDAC circuit.
 18. The circuit ofclaim 17 further comprising a monitor circuit coupled to a second outputof said first delta-sigma modulator circuit that monitors the secondoutput of said first delta-sigma modulator circuit to determine when thefault condition occurs.
 19. The circuit of claim 17 further comprising amonitor circuit coupled to a second output of said second delta-sigmamodulator circuit that monitors the second output of said seconddelta-sigma modulator circuit to determine when the circuit recoversfrom the fault condition.
 20. The circuit of claim 1 wherein said pulsecode modulator circuit further comprises a second delta-sigma modulatorcircuit coupled to a first output of the reconfigurable circuit and tothe output node.
 21. The circuit of claim 20 wherein said pulse codemodulator circuit further comprises a digital differentiator circuitcoupled to a first output of the second delta-sigma modulator circuit.22. The circuit of claim 21 further comprising a first delay circuitcoupled to the input node and the first MDAC circuit.
 23. The circuit ofclaim 22 wherein said demodulator circuit further comprises a secondMDAC circuit coupled to the first delay circuit and to an output of thedigital differentiator circuit, and a subtractor circuit coupled to anoutput of the first MDAC circuit, an output of the second MDAC circuit,and the output node.
 24. The circuit of claim 1 further comprising amonitor circuit coupled to an output of said reconfigurable circuitconfigured as the first delta-sigma modulator circuit that monitors theoutput of said first delta-sigma modulator circuit to determine when thefault condition occurs.
 25. The circuit of claim 20 further comprising amonitor circuit coupled to an output of said second delta-sigmamodulator circuit that monitors the output of said second delta-sigmamodulator circuit to determine when the circuit recovers from the faultcondition.
 26. The circuit of claim 23 further comprising a monitorcircuit coupled to the first MDAC circuit and a second output of saidreconfigurable circuit configured as the first delta-sigma modulatorcircuit that monitors the output of said first delta-sigma modulatorcircuit to determine when the fault condition occurs.
 27. The circuit ofclaim 23 further comprising a monitor circuit coupled to the first MDACcircuit and a second output of said second delta-sigma modulator circuitthat monitors the second output of said second delta-sigma modulatorcircuit to determine when the circuit recovers from the fault condition.28. The circuit of claim 26 wherein the monitor circuit is furthercoupled to a second output of the second delta-sigma modulator circuit.29. The circuit of claim 27 wherein the monitor circuit is furthercoupled to a second output of the reconfigurable circuit configured asthe comparator circuit.
 30. The circuit of claim 28 wherein saiddemodulator circuit further comprises a multiplier coupled between theoutput of the second MDAC circuit and the subtractor circuit.
 31. Thecircuit of claim 30 further comprising a second delay circuit coupled tothe first delay circuit and the second MDAC circuit.
 32. The circuit ofclaim 20 further comprising a monitor circuit coupled to a second outputof the reconfigurable circuit and to an output of said seconddelta-sigma modulator circuit, wherein at least one of the conditionsfrom the group consisting of the following is true: 1) the monitorcircuit monitors the second output of the reconfigurable circuitconfigured as the first delta-sigma modulator circuit to determine whenthe fault condition occurs and 2) the monitor circuit monitors theoutput of said second delta-sigma modulator circuit to determine whenthe circuit recovers from the fault condition.
 33. A circuit forproviding an output signal at an output node proportional to aroot-mean-square (RMS) value of an input signal at an input node,wherein the circuit is capable of detecting and independently recoveringfrom a fault condition and includes a first delta-sigma modulator and asecond delta-sigma modulator, the circuit comprising: a reconfigurablecircuit coupled to the input node and the output node; the seconddelta-sigma modulator coupled to the output node and a first output ofthe reconfigurable circuit; and a monitor circuit coupled to a secondoutput of the reconfigurable circuit and a first output of the seconddelta-sigma modulator, wherein the monitor circuit monitors one of theoutputs from the group consisting of the following: 1) the output of thereconfigurable circuit when the reconfigurable circuit is configured asthe first delta-sigma modulator to detect when the fault conditionexists, and 2) the output of the second delta-sigma modulator when thereconfigurable circuit is configured as a comparator to detect when thecircuit recovers from the fault condition.
 34. The circuit of claim 33wherein the monitor circuit is configured to generate a first controlsignal that causes the reconfigurable circuit to be configured as thecomparator.
 35. The circuit of claim 34 wherein the monitor circuit isconfigured to generate a second control signal that causes thereconfigurable circuit to be configured as the first delta-sigmamodulator.
 36. The circuit of claim 33 further comprising a switchcoupled between the reconfigurable circuit and the output node.
 37. Thecircuit of claim 33 further comprising a demodulator circuit coupled toan output of the monitor circuit, the input node, and the output node.38. The circuit of claim 37 further comprising a delay circuit coupledbetween the input node and the demodulator circuit.
 39. A circuit forproviding an output signal at an output node proportional to aroot-mean-square (RMS) value of an input signal at an input node,wherein the circuit is capable of detecting and independently recoveringfrom a fault condition, the circuit comprising: a reconfigurable circuitcoupled to the input node and the output node; and a monitor circuitcoupled to an output of the reconfigurable circuit to detect a faultcondition, wherein the reconfigurable circuit comprises an amplifier, acomparator, a plurality of capacitors, and a plurality of switches. 40.The circuit of claim 39 wherein the monitor circuit generates a firstcontrol signal when a fault condition is detected that couples the inputnode to a first input of the amplifier and a first output of theamplifier, and the output node to a second input of the amplifier and asecond output of the amplifier.
 41. A circuit for providing an outputsignal at an output node proportional to-a root-mean-square (RMS) valueof an input signal at an input node, wherein the circuit includescircuitry capable of detecting and independently recovering from a faultcondition.